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atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 features ? low voltage operation ? 1.7v (v cc = 1.7v to 3.6v) ? internally organized 128 x 8 (1k) or 256 x 8 (2k) ? i 2 c-compatible (2-wire) serial interface ? schmitt triggers, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 400khz (1.7v) and 1mhz (2.5v) compatibility ? write protect pin for full array hardware data protection ? ultra low active current (1ma max) and standby current (0.8 a max) ? 8-byte page write mode ? partial page writes allowed ? random and sequential read modes ? self-timed write cycle within 5ms max ? high reliability ? endurance: 1,000,000 write cycles ? data retention: 100 years ? green package options (lead-free/halide-free/rohs compliant) ? 8-lead soic, 8-lead tssop, 8-pad udfn, 8-lead pdip, (1) 5-lead sot23, and 8-ball vfbga ? die sale options: wafer form and tape and reel available description the atmel ? at24c01d/02d provides 1,024/2,048 bits of serial electrically erasable and programmable read-only memory (eeprom) organized as 128/256 words of eight bits each. the device?s cascadable feature allows up to eight devices to share a common 2-wire bus. these device are optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. both devices are available in space-saving 8-lead soic, 8-lead tssop, 8-pad udfn, 8-lead pdip, (1) 5-lead sot23, and 8-ball vfbga packages. the entire family of packages operates from 1.7v to 3.6v. note: 1. contact atmel sales for availability of this package. at24c01d and at24c02d i 2 c-compatible (2-wire) serial eeprom 1-kbit (128 x 8) or 2-kbit (256 x 8) datasheet
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 2 1. pin descriptions and pinouts table 1-1. pin descriptions note: 1. if the a 0 , a 1 , a 2 , or wp pins are not driven, they are internally pulled down to gnd. in order to operate in a wide variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong. once these pins are biased above the cmos input buffer?s trip point (~0.5 x v cc ), the pull-down mechanism disengages. atmel recommends connecting these pins to a known state whenever possible. note: 1. refer to ?device addressing? on page 7 for details about addressing the sot23 version of the device. pin number pin symbol pin name and functional description asserted state pin type 1, 2, 3 a 0 , a 1 , a 2 device address inputs: the a 0 , a 1 , and a 2 pins are used to select the hardware device address and correspond to the seventh, sixth, and fifth bit of the i 2 c seven bit slave address. these pins can be directly connected to v cc or gnd, allowing up to eight devices on the same bus. refer to note 1 for behavior of the pin when not connected. ? input 4 gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ? power 5 sda serial data: the sda pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. the sda pin must be pulled-high using an external pull-up resistor (not to exceed 10k ? in value) and may be wire-ored with any number of other open-drain or open-collector pins from other devices on the same bus. ? input/ output 6 scl serial clock: the scl pin is used to provide a clock to the device and to control the flow of data to and from the device. command and input data present on the sda pin is always latched in on the rising edge of scl, while output data on the sda pin is clocked out on the falling edge of scl. the scl pin must either be forced high when the serial bus is idle or pulled-high using an external pull-up resistor. ? input 7 wp write protect: connecting the wp pin to gnd will ensure normal write operations.when the wp pin is connected to vcc, all write operations to the memory are inhibited. refer to note 1 for behavior of the pin when not connected. high input 8 v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ? power a 0 a 1 a 2 gnd v cc wp scl sda 8-lead soic top view note: package drawings are not to scale 8 7 6 5 8-lead tssop top view 1 2 3 4 8 7 6 5 a 0 a 1 a 2 gnd v cc wp scl sda top view 8 7 6 5 1 2 3 4 8-pad udfn a 0 a 1 a 2 gnd v cc wp scl sda v cc wp scl sda a 0 a 1 a 2 gnd 1 2 3 4 8 7 6 5 8-ball vfbga top view top view scl gnd sda wp v cc 5-lead sot23 (1) 1 2 3 5 4 1 2 3 4 top view 8-lead pdip a 0 a 1 a 2 gnd v cc wp scl sda 8 7 6 5 1 2 3 4
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 3 2. device block diagram 1 page start stop detector gnd a 2 memory system control module high voltage generation circuit data & ack input/output control address register and counter write protection control d out d in hardware address comparator v cc wp scl sda power on reset generator eeprom array column decoder row decoder data register a 1 a 0
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 4 3. device operation and communication the at24c01d/02d operates as a slave device and utilizes a simple i 2 c-compatible 2-wire digital serial interface to communicate with a host controller, commonly referred to as the bus master. the master initiates and controls all read and write operations to the slave devices on the serial bus, and both the master and the slave devices can transmit and receive data on the bus. the serial interface is comprised of just two signal lines: serial clock (scl) and serial data (sda). the scl pin is used to receive the clock signal from the master, while the bidirectional sda pin is used to receive command and data information from the master as well as to send data back to the master. data is always latched into the at24c01d/02d on the rising edge of scl and always output from the device on the falling edge of scl. both the scl and sda pin incorporate integrated spike suppression filters and schmitt triggers to minimize the effects of input spikes and bus noise. all command and data information is transferred with the most-significant bit (msb) first. during bus communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have been transferred, the receiving device must respond with either an acknowledge (ack) or a no-acknowledge (nack) response bit during a ninth clock cycle (ack/nack clock cycle) generated by the master; therefore, nine clock cycles are required for every one byte of data transferred. there are no unused clock cycles during any read or write operation, so there must not be any interruptions or breaks in the data stream during each data byte transfer and ack or nack clock cycle. during data transfers, data on the sda pin must only change while scl is low, and the data must remain stable while scl is high. if data on the sda pin changes while scl is high, then either a start or a stop condition will occur. start and stop conditions are used to initiate and end all serial bus communication between the master and the slave devices. the number of data bytes transferred between a start and a stop condition is not limited and is determined by the master. in order for the serial bus to be idle, both the scl and sda pins must be in the logic-high state at the same time. 3.1 clock and data transition requirements the sda pin is an open drain terminal and therefore must be pulled high with an external pull-up resistor. data on the sda pin may change only during scl low time periods. data changes during scl high periods will indicate a start or stop condition as defined below. 3.2 start and stop conditions 3.2.1 start condition a start condition occurs when there is a high-to-low transition on the sda pin while the scl pin is at a stable logic 1 state and will bring the device out of standby mode. the master uses a start condition to initiate any data transfer sequence; therefore, every command must begin with a start condition. the device will continuously monitor the sda and scl pins for a start condition but will not respond unless one is detected. see figure 3-1 for more details. 3.2.2 stop condition a stop condition occurs when there is a low-to-high transition on the sda pin while the scl pin is stable in the logic 1 state. the master can use the stop condition to end a data transfer sequence with the at24c01d/02d which will subsequently return to standby mode. the master can also utilize a repeated start condition instead of a stop condition to end the current data transfer if the master will perform another operation. see figure 3-1 for more details.
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 5 3.3 acknowledge and no-acknowledge after every byte of data is received, the receiving device must confirm to the master that it has successfully received the data byte by responding with what is known as an acknowledge (ack). an ack is accomplished by the transmitting device first releasing the sda line at the falling edge of the eighth clock cycle followed by the receiving device responding with a logic 0 during the entire high period of the ninth clock cycle. when the at24c01d/02d is transmitting data to the master, the master can indicate that it is done receiving data and wants to end the operation by sending a logic 1 response to the at24c01d/02d instead of an ack response during the ninth clock cycle. this is known as a no-acknowledge (nack) and is accomplished by the master sending a logic 1 during the ninth clock cycle, at which point the at24c01d/02d will release the sda line so the master can then generate a stop condition. the transmitting device, which can be the bus master or the serial eeprom, must release the sda line at the falling edge of the eighth clock cycle to allow the receiving device to drive the sda line to a logic 0 to ack the previous 8-bit word. the receiving device must release the sda line at the end of the ninth clock cycle to allow the transmitter to continue sending new data. a timing diagram has been provided in figure 3-1 to better illustrate these requirements. figure 3-1. start condition, data transitions, stop condition and acknowledge 3.4 standby mode the at24c01d/02d features a low power standby mode which is enabled when any one of the following occurs: ? a valid power-up sequence is performed (see section 8.6, ?power-up requirements and reset behavior? ). ? a stop condition is received by the device unless it initiates an internal write cycle (see section 5. ). ? at the completion of an internal write cycle (see section 5., ?write operations? ). ? an unsuccessful match of the device type identifier or hardware address in the device address byte occurs (see section 4.1, ?device addressing? ). ? the bus master does not ack the receipt of data read out from the device; instead it sends a nack response (see section 6., ?read operations? ). scl sda sda must be stable sda change allowed sda change allowed acknowledge valid stop condition start condition 12 89 sda must be stable acknowledge window the transmitting device (master or slave) must release the sda line at this point to allow the receiving device (master or slave) to drive the sda line low to ack the previous 8-bit word. the receiver (master or slave) must release the sda line at this point to allow the transmitter to continue sending new data.
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 6 3.5 software reset after an interruption in protocol, power loss, or system reset, any 2-wire part can be protocol reset by following these steps: 1. create a start condition, 2. clock nine cycles, 3. create another start condition followed by a stop condition as seen in figure 3-2 . the device will be ready for the next communication after above steps have been completed. figure 3-2. software reset scl 9 start condition start condition stop condition 8 3 2 1 sda dummy clock cycles
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 7 4. memory organization the at24c01d is internally organized as 16 pages of 8 bytes each while the at24c02d is organized as 32 pages of 8 bytes each. 4.1 device addressing accessing the device requires an 8-bit device address word following a start condition to enable the device for a read or write operation. since multiple slave devices can reside on the serial bus, each slave device must have its own unique address so that the master can access each device independently. the most significant four bits of the device address word is referred to as the device type identifier. the device type identifier ? 1010 ? (ah) is required in bits seven through four of the device address byte (see table 4-1 .) following the 4-bit device type identifier are the hardware slave address bits, a 2 , a 1 , and a 0 . these bits can be used to expand the address space by allowing up to eight other serial eeprom devices on the same bus. the a 2 , a 1 , and a 0 values must correlate with the voltage level on the corresponding hardwired input pins, a 2 , a 1 , and a 0 . these hardwired address pins use an internal proprietary circuit that automatically biases each pin to a logic 0 state if the pin is allowed to float. in order to operate in a wide variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong. once the pin is biased above the cmos input buffer?s trip point (~0.5 x v cc ), the pull-down mechanism disengages. atmel recommends connecting the a 2 , a 1 , and a 0 pins to a known state whenever possible. when using the sot23 package, the a 2 , a 1 , and a 0 signals are not accessible and are left floating. the previously mentioned automatic pull-down circuit will set these signals to a logic 0 state. as a result, to properly communicate with the device in the sot23 package, the a 2 , a 1 , and a 0 software bits must always be set to logic 0 for any operation. this requirement has been shown in table 4-1 . the eighth bit of the device address (bit 0) is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon the successful comparison of the device address, the eeprom will return an ack. if a valid comparison is not made, the device will nack and return to a standby state. table 4-1. device address byte for all operations except the current address read, a word address byte must be transmitted to the device immediately following the device address byte. the word address byte contains a 7-bit (in the case of the at24c01d) or 8-bit (in the case of the at24c02d) memory array address, and is used to specify which location in the eeprom to start reading or writing. please refer to table 4-2 to review these bit positions. table 4-2. word address byte note: 1. the a7 bit is a don?t care bit for the at24c01d. the relationship of the ac timing parameters with respect to scl and sda for the at24c01d/02d are shown in the timing waveform in figure 8-1 on page 14 . the ac timing characteristics and specifications are outlined in section 8.4 ?ac characteristics? on page 14 . package device type identifier hardware slave address bits read/ write bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 soic, tssop, udfn, pdip, vfbga 1 0 1 0 a 2 a 1 a 0 r/ w sot23 1 0 1 0 0 0 0 r/ w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a7 (1) a6 a5 a4 a3 a2 a1 a0
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 8 5. write operations all write operations for the at24c01d/02d begin with the master sending a start condition, followed by a device address byte with the r/ w bit set to ? 0 ? , and then by the word address byte. the data value(s) to be written to the device immediately follow the word address byte. 5.1 byte write the at24c01d/02d supports the writing of single 8-bit bytes. selecting a data word in the 1-kbit memory requires a 7-bit word address while selecting a data word in the 2-kbit memory requires an 8-bit word address. upon receipt of the proper device address and word address bytes, the eeprom will send an acknowledge. the device will then be ready to receive the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will respond with an acknowledge. the addressing device, such as a bus master, must then terminate the write operation with a stop condition. at that time the eeprom will enter an internally self-timed write cycle, which will complete within a time of t wr , while the data is being programmed into the nonvolatile eeprom. all inputs are disabled during this write cycle, and the eeprom will not respond until the write is complete. figure 5-1. byte write 5.2 page write a page write operation allows up to eight bytes to be written in the same write cycle, provided all bytes are in the same row of the memory array (where address bits a7 through a3 are the same). partial page writes of less than eight bytes are also allowed. a page write is initiated the same way as a byte write, but the bus master does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the bus master can transmit up to seven additional data words. the eeprom will respond with an ack after each data word is received. once all data to be written has been sent to the device, the bus master must issue a stop condition (see figure 5-2 ) at which time the internally self-timed write cycle will begin. the lower three bits of the word address are internally incremented following the receipt of each data word. the higher order address bits are not incremented and retains the memory page row location. page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. when the incremented word address reaches the page boundary, the address counter will ?roll-over? to the beginning of the same page. nevertheless, creating a roll-over event should be avoided as previously loaded data in the page could become unintentionally altered. scl sda device address byte word address byte data word start by master ack from slave msb msb stop by master msb 1 2 3 4 5 6 7 8 9 1 0 1 0 a 2 a 1 a 0 0 0 1 2 3 4 5 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 d0 0 a7 a6 a5 a4 a3 a2 a1 a0 0 1 2 3 4 5 6 7 8 9 ack from slave ack from slave
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 9 figure 5-2. page write 5.3 acknowledge polling an acknowledge polling routine can be implemented to optimize time sensitive applications that would prefer not to wait the fixed maximum write cycle time (t wr ). this method allows the application to know immediately when the serial eeprom write cycle has completed, so a subsequent operation can be started. once the internally self-timed write cycle has started, an acknowledge polling routine can be initiated. this involves repeatedly sending a start condition followed by a valid device address byte with the r/ w bit set at logic 0. the device will not respond with an ack while the write cycle is ongoing. once the internal write cycle has completed, the eeprom will respond with an ack, allowing a new read or write operation to be immediately initiated. a flow chart has been included below in figure 5-3 to better illustrate this technique. figure 5-3. acknowledge polling flow chart scl sda start by master ack from slave ack from slave device address byte word address byte msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a 2 a 1 a 0 0 0 ack from slave stop by master ack from slave data word (n) data word (n+x), max of 8 without rollover 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 msb msb a7 a6 a5 a4 a3 a2 a1 a0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 did the device ack? send any write protocol send stop condition to initiate the write cycle send start condition followed by a valid device address byte with r/w = 0 proceed to next read or write operation no yes
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 10 5.4 write cycle timing the length of the self-timed write cycle, or t wr , is defined as the amount of time from the stop condition that begins the internal write operation, to the start condition of the first device address byte sent to the at24c01d/02d which it subsequently responds to with an ack. figure 5-4 has been included to show this measurement. during the internally self-timed write cycle, any attempts to read or write to the memory array will not be processed. figure 5-4. write cycle timing 5.5 write protection the at24c01d/02d utilizes a hardware data protection scheme that allows the user to write protect the entire memory contents when the wp pin is at v cc (or a valid v ih ). no write protection will be set if the wp pin is at gnd or left floating. table 5-1. at24c01d/02d write protect behavior the status of the wp pin is sampled at the stop condition for every byte write or page write command prior to the start of an internally self-timed write operation. changing the wp pin state after the stop condition has been sent will not alter or interrupt the execution of the write cycle. the wp pin state must be valid with respect to the associated setup (t su.wp ) and hold (t hd.wp ) as shown in the figure 5-5 below. the wp setup time is the amount of time that the wp state must be stable before the stop condition is issued. the wp hold time is the amount of time after the stop condition that the wp state must remain stable. if an attempt is made to write to the device while the wp pin has been asserted, the device will acknowledge the device address, word address, and data bytes but no write cycle will occur when the stop condition is issued, and the device will immediately be ready to accept a new read or write command. figure 5-5. write protect setup and hold timing t wr stop condition start condition data word n ack d0 sda stop condition scl 89 ack first acknowledge from the device to a valid device address sequence after write cycle is initiated. the minumum t wr can only be determined through the use of an ack polling routine. 9 wp pin voltage part of the array protected v cc full array gnd none ? write protection not enabled scl sda in 1 2 7 8 9 d7 d6 d1 d0 wp t su.wp stop by master data word input sequence page/byte write operation ack by slave t hd.wp
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 11 6. read operations read operations are initiated the same way as write operations with the exception the read/write select bit in the device address word must be a logic 1. there are three read operations: ? current address read ? random address read ? sequential read 6.1 current address read the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the v cc is maintained to the part. the address roll-over during read is from the last byte of the last page to the first byte of the first page of the memory. a current address read operation will output data according to the location of the internal data word address counter. this is initiated with a start condition, followed by a valid device address byte with the r/ w bit set to logic 1. the device will ack this sequence and the current address data word is serially clocked out on the sda line. all types of read operations will be terminated if the bus master does not respond with an ack (it nacks) during the ninth clock cycle. a read instruction may be terminated at any point with a stop condition which will force the device into standby mode. figure 6-1. current address read 6.2 random read a random read begins in the same way as a byte write operation does to load in a new data word address. this is known as a ?dummy write? sequence. however, the data byte and the stop condition of the byte write must be omitted to prevent the part from entering an internal write cycle. once the device address and word address are clocked in and acknowledged by the eeprom, the bus master must generate another start condition. the bus master now initiates a current address read by sending a start condition, followed by a valid device address byte with the r/w bit set to logic 1. the eeprom will ack the device address and serially clock out the data word on the sda line. all types of read operations will be terminated if the bus master does not respond with an ack (it nacks) during the ninth clock cycle. a read instruction may be terminated at any point with a stop condition which will force the device into standby mode. scl sda device address byte data word (n) start by master ack from slave nack from master stop by master msb msb 1 0 1 0 a 2 a 1 a 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 12 figure 6-2. random read 6.3 sequential read sequential reads are initiated by either a current address read or a random read. after the bus master receives a data word, it responds with an acknowledge. as long as the eeprom receives an ack, it will continue to increment the word address and serially clock out sequential data words. figure 6-3 depicts a sequential read sequence that was initiated as a current address read. when the maximum memory address is reached, the data word address will ?roll over? and the sequential read will continue from the beginning of the memory array. all types of read operations will be terminated if the bus master does not respond with an ack (it nacks) during the ninth clock cycle. a read instruction may be terminated at any point with a stop condition which will force the device into standby mode. figure 6-3. sequential read, initiated by a current address read 7. device default condition from atmel the at24c01d/02d is delivered with the eeprom array set to logic 1, resulting in ffh data in all locations. scl sda start by master device address byte word address byte msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a 2 a 1 a 0 0 0 dummy write start by master device address byte data word (n) stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a 2 a 1 a 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 1 a7 a6 a5 a4 a3 a2 a1 a0 0 ack from slave ack from slave ack from slave nack from master scl sda start by master ack from slave ack from master device address byte data word (n) msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a 2 a 1 a 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 0 ack from master nack from master stop by master ack from master data word (n+1) data word (n+2) data word (n+x) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 1 msb msb msb
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 13 8. electrical specifications 8.1 absolute maximum ratings 8.2 dc and ac operating range 8.3 dc characteristics notes: 1. typical values characterized at t a = +25c unless otherwise noted. 2. this parameter is characterized but is not 100% tested in production. temperature under bias . . . . . . . . . .?55 ? c to +125 ? c storage temperature . . . . . . . . . . . .?65 ? c to +150 ? c supply voltage with respect to ground . . . . . . . . . . . . ?0.5v to +4.10v voltage on any pin with respect to ground . . . . . . . . . ?0.6v to v cc + 0.5v dc output current. . . . . . . . . . . . . . . . . . . . . . . 5.0ma functional operation at the ?absolute maximum ratings? or any other conditions beyond those indicated in section 8.2 ?dc and ac operating range? is not implied or guaranteed. stresses beyond those listed under ?absolute maximum ratings? and/or exposure to the ?absolute maximum ratings? for extended periods may affect device reliability and cause permanent damage to the device. the voltage extremes referenced in the ?absolute maximum ratings? are intended to accommodate short duration undershoot/overshoot pulses that the device may be subjected to during the course of normal operation and does not imply or guarantee functional device operation at these levels for any extended period of time. at24c01d and at24c02d operating temperature (case) industrial temperature range ?40 ? c to +85 ? c v cc power supply low voltage grade 1.7v to 3.6v parameters are applicable over the operating range in section 8.2 , unless otherwise noted. symbol parameter test condition min typical (1) max units v cc supply voltage 1.7 3.6 v i cc1 supply current, read v cc = 1.8v (2) read at 400khz 0.08 0.3 ma v cc = 3.6v read at 1mhz 0.15 0.5 ma i cc2 supply current, write v cc = 3.6v write at 1mhz 0.20 1.0 ma i sb standby current v cc = 1.8v (2) v in = v cc or v ss 0.08 0.4 a v cc = 3.6v 0.10 0.8 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (2) ?0.6 v cc x 0.3 v v ih input high level (2) v cc x 0.7 v cc + 0.5 v v ol1 output low level v cc = 1.7v i ol = 0.15ma 0.2 v v ol2 output low level v cc = 3.0v i ol = 2.1ma 0.4 v
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 14 8.4 ac characteristics notes: 1. these parameters are determined through product characterization and are not tested 100% in production. 2. ac measurement conditions: ? c l : 100pf ? r pup (bus line pull-up resistor to v cc ): 1.3 k ? (1000khz), 4k ? (400khz) ? input pulse voltages: 0.3 v cc to 0.7 v cc ? input rise and fall times: ? 50ns ? input and output timing reference voltages: 0.5 x v cc figure 8-1. bus timing parameters are applicable over operating range in section 8.2 , unless otherwise noted. test conditions shown in note 2 . symbol parameter v cc ??? 1.7v - 3.6v v cc ? 2.5v - 3.6v units min max min max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1300 500 ns t high clock pulse width high 600 400 ns t i input filter spike suppression (scl,sda) (1) 100 100 ns t aa clock low to data out valid 900 450 ns t buf bus free time between stop and start (1) 1300 500 ns t hd.sta start hold time 600 250 ns t su.sta start set-up time 600 250 ns t hd.dat data in hold time 0 0 ns t su.dat data in set-up time 100 100 ns t r inputs rise time (1) 300 100 ns t f inputs fall time (1) 300 100 ns t su.sto stop set-up time 600 250 ns t su.wp write protect setup time 600 100 ns t hd.wp write protect hold time 600 400 ns t dh data out hold time 50 50 ns t wr write cycle time 5 5 ms scl sda in sda out t f t high t low t r t aa t dh t buf t su.sto t su.dat t hd.dat t hd.sta t su.sta
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 15 8.5 pin capacitance (1) note: 1. this parameter is characterized but is not 100% tested in production. 8.6 power-up requirements and reset behavior during a power-up sequence, the v cc supplied to the at24c01d/02d should monotonically rise from gnd to the minimum v cc level as specified in section 8.2 with no greater than a slew rate of 1v/ s. 8.6.1 device reset to prevent write operations or other spurious events from happening during a power-up sequence, the at24c01d/02d includes a power-on-reset (por) circuit. upon power-up, the device will not respond to any commands until the v cc level crosses the internal voltage threshold (v por ) that brings the device out of reset and into standby mode. the system designer must ensure that instructions are not sent to the device until the v cc supply has reached a stable value greater than or equal to the minimum v cc level. additionally, once the v cc is greater than or equal to the minimum v cc level, the bus master must wait at least t pup before sending the first command to the device. see table 8-1 for the values associated with these power-up parameters. table 8-1. power-up conditions if an event occurs in the system where the v cc level supplied to the at24c01d/02d drops below the maximum v por level specified, it is recommended that a full power cycle sequence be performed by first driving the v cc pin to gnd, waiting at least the minimum t poff time, and then performing a new power-up sequence in compliance with the requirements defined in this section. 8.7 eeprom cell performance characteristics notes: 1. write endurance performance is determined through characterization and the qualification process. 2. the data retention capability is determined through qualification and checked on each device in production. applicable over recommended operating range from t a = 25 ? c, f = 1.0mhz, v cc = 3.6v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v symbol parameter min max units t pup time required after v cc is stable before the device can accept commands. 100 s v por power-on reset threshold voltage 1.5 v t poff minimum time at v cc = 0v between power cycles. 1 ms operation test condition min max units write endurance (1) t a = 25c, v cc (min)< v cc at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 16 9. ordering code detail atmel designator product family 24c = standard serial eeprom device density shipping carrier option package device grade or wafer/die thickness package option 01 = 1 kilobit 02 = 2 kilobit t = tape and reel b = bulk (tubes) operating voltage m = 1.7v to 3.6v h = green, nipdau lead finish industrial temperature range (-40c to +85c) u = green, matte tin lead finish or snagcu ball industrial temperature range (-40c to +85c) 11 = 11mil wafer thickness ss = jedec soic x = tssop ma = 2.0mm x 3.0mm udfn p = pdip st = sot23 c = vfbga wwu = wafer unsawn at24c01d-sshm-t device revision
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 17 10. ordering information notes: 1. t = tape and reel: ? soic = 4k units per reel ? tssop, udfn, and sot23 = 5k units per reel 2. b = bulk ? soic and tssop = 100 units per tube ? pdip = 50 units per tube 3. for wafer sales, please contact atmel sales. atmel ordering code lead finish package voltage operation range at24c01d-sshm-t (1) nipdau (lead-free/halogen-free) 8s1 1.7v to 3.6v industrial temperature (?40 ? c to 85 ? c) at24c01d-sshm-b (2) at24c01d-xhm-t (1) 8x at24c01d-xhm-b (2) at24c01d-mahm-t (1) 8ma2 at24c01d-pum matte tin (lead-free/halogen-free) 8p3 at24c01d-stum-t (1) 5ts1 at24c01d-cum-t (1) snagcu ball (lead-free/halogen-free) 8u3-1 at24c01d-wwu11m (3) n/a wafer sale at24c02d-sshm-t (1) nipdau (lead-free/halogen-free) 8s1 1.7v to 3.6v industrial temperature (?40 ? c to 85 ? c) at24c02d-sshm-b (2) at24c02d-xhm-t (1) 8x at24c02d-xhm-b (2) at24c02d-mahm-t (1) 8ma2 at24c02d-pum matte tin (lead-free/halogen-free) 8p3 at24c02d-stum-t (1) 5ts1 at24c02d-cum-t (1) snagcu ball (lead-free/halogen-free) 8u3-1 at24c02d-wwu11m (3) n/a wafer sale package type 8s1 8-lead, 0.15? wide, plastic gull wing small outline (jedec soic) 8x 8-lead, 4.40mm body, plastic thin shrink small outline package (tssop) 8ma2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, ultra thin dual flat no lead (udfn) 8p3 8-lead, 0.30? wide, plastic dual inline package (pdip) 5ts1 5-lead, 2.90mm x 1.60mm body, plastic thin shrink small outline (sot23) 8u3-1 8-ball, 1.50mm x 2.00mm body, 0.5mm pitch, very thin fine ball grid array (vfbga)
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 18 11. part markings drawing no. rev. title 24c01-02dsm d 12/20/13 24c01-02dsm , at24c01d and at24c02d package marking information package mark contact: dl-cso-assy_eng@atmel.com aaaaaaaa ###% @ atmlhyww 8-lead soic 8-lead tssop aaaaaaa ###% @ athyww 8-pad udfn ### h%@ yxx 2.0 x 3.0 mm body note 2: package drawings are not to scale note 1: designates pin 1 at24c01d and at24c02d: package marking information catalog number truncation at24c01d truncation code ###: 01d at24c02d truncation code ###: 02d date codes voltages y = year m = month ww = work week of assembly % = minimum voltage 3: 2013 7: 2017 a: january 02: week 2 m: 1.7v min 4: 2014 8: 2018 b: february 04: week 4 5: 2015 9: 2019 ... ... 6: 2016 0: 2020 l: december 52: week 52 country of assembly lot number grade/lead finish material @ = country of assembly aaa...a = atmel wafer lot number h: industrial/nipdau u: industrial/matte tin/snagcu trace code atmel truncation xx = trace code (atmel lot numbers correspond to code) at: atmel example: aa, ab.... yz, zz atm: atmel atml: atmel ###%u ymxx bottom mark top mark 5-lead sot-23 1.5 x 2.0 mm body 8-ball vfbga pin 1 ###u ymxx 8-lead pdip aaaaaaaa ###% @ atmluyww
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 19 12. packaging information 12.1 8s1 ? 8-lead jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: packagedrawings@atmel.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 20 12.2 8x ? 8-lead tssop drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side view end view top view a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. package drawing contact: packagedrawings@atmel.com h 8x e 12/8/11 8x, 8-lead 4.4mm body, plastic thin shrink small outline package (tssop) tnr c a1
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 21 12.3 8ma2 ? 8-pad udfn drawing no. rev. title gpc 8ma2 e 12/20/13 8ma2, 8-pad 2 x 3 x 0.6mm body, thermally enhanced plastic ultra thin dual flat no-lead package (udfn) ynz common dimensions (unit of measure = mm) symbol min nom max note a 0.50 0.55 0.60 a1 0.0 0.02 0.05 a2 - - 0.55 d 1.90 2.00 2.10 d1 1.20 - 1.60 e 2.90 3.00 3.10 e1 1.20 - 1.60 b 0.18 0.25 0.30 3 c 1.52 ref l 0.30 0.35 0.40 e 0.50 bsc k 0.20 - - top view side view bottom view package drawing contact: packagedrawings@atmel.com c e pin 1 id d 8 7 6 5 1 2 3 4 a a1 a2 d2 e2 e (6x) l (8x) b (8x) pin#1 id k 1 2 3 4 8 7 6 5 notes: 1. this drawing is for general information only. refer to drawing mo-229, for proper dimensions, tolerances, datums, etc. 2. the pin #1 id is a laser-marked feature on top view. 3. dimensions b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 4. the pin #1 id on the bottom view is an orientation feature on the thermal pad.
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 22 12.4 8p3 ? 8-lead pdip drawing no. rev. title gpc notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view package drawing contact: packagedrawings@atmel.com 8p3 d 06/21/11 8p3, 8-lead, 0.300? wide body, plastic dual in-line package (pdip) ptc
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 23 12.5 5st1 ? 5-lead sot23 drawing no. rev. title gpc package drawing contact: packagedrawings@atmel.com 5ts1 d 5/31/12 5ts1, 5-lead 1.60mm body, plastic thin shrink small outline package (shrink sot) tsz common dimensions (unit of measure = mm) symbol min nom max note a - - 1.00 a1 0.00 - 0.10 a2 0.70 0.90 1.00 c 0.08 - 0.20 3 d 2.90 bsc 1,2 e 2.80 bsc 1,2 e1 1.60 bsc 1,2 l1 0.60 ref e 0.95 bsc e1 1.90 bsc b 0.30 - 0.50 3,4 1. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.15 mm per side. 2. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. these dimensions apply to the flat section of the lead between 0.08 mm and 0.15 mm from the lead tip. 4. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the foot. minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. this drawing is for general information only. refer to jedec drawing mo-193, variation ab for additional information. 5 4 2 l1 l c end view c a a2 a1 b e plane seating d side view e e1 e1 3 1 top view
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 24 12.6 8u3-1 ? 8-ball vfbga drawing no. rev. title gpc package drawing contact: packagedrawings@atmel.com 8u3-1 f 6/11/13 8u3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, very thin, fine-pitch ball grid array package (vfbga) gxu common dimensions (unit of measure - mm) symbol min nom max note a 0.73 0.79 0.85 a1 0.09 0.14 0.19 a2 0.40 0.45 0.50 b 0.20 0.25 0.30 2 d 1.50 bsc e 2.0 bsc e 0.50 bsc e1 0.25 ref d 1.00 bsc d1 0.25 ref 1. this drawing is for general information only. 2. dimension ?b? is measured at maximum solder ball diameter. 3. solder ball composition shall be 95.5sn-4.0ag-.5cu. notes: a2 side view a pin 1 ball pad corner top view e d a1 b 8 solder balls bottom view (d1) d 4 3 2 (e1) 6 e 5 7 pin 1 ball pad corner 1 8 2.
at24c01d and at24c02d [datasheet] atmel-8871b-seeprom-at24c01d-02d-datasheet_032014 25 13. revision history doc. no. date comments 8871b 03/2014 correct pinouts from bottom to top view and grammatical changes. no changes to functional specification. 8871a 12/2013 initial document release.
x x x x x x atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 | www.atmel.com ? 2014 atmel corporation. / rev.: atmel-8871b-seeprom-at24c01d-02d-datasheet_032014. atmel ? , atmel logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiar ies. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and condit ions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its p roducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limi tation, damages for loss and profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. atmel d oes not make any commitment to update the information contained herein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automo tive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety-critical, military, and automotive applications disclaimer: atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (?safety-critical a pplications?) without an atmel officer's specific written consent. safety-critical applications include, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military-grade. atmel products are not designed nor intended for use in automotive applications unless specifically designated by atmel as automotive-grade.

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